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| author | Maxim Cournoyer <maxim.cournoyer@gmail.com> | 2024-11-12 14:17:13 +0900 |
|---|---|---|
| committer | Maxim Cournoyer <maxim.cournoyer@gmail.com> | 2024-11-12 17:41:38 +0900 |
| commit | 744e8f7d046a07e4559b1e66bcb4683a197873ff (patch) | |
| tree | 8aced43b3186e939536288aeeaf45eb7beab38ea /gnu/packages/fpga.scm | |
| parent | 2bad254d032fca2843ffdaff401619c7cecc7c5a (diff) | |
gnu: yosys: Sort inputs.
* gnu/packages/fpga.scm (yosys): Sort inputs.
Change-Id: I5a4c97b84ae1e5b7f08b82858c47542fdcfd37b1
Diffstat (limited to 'gnu/packages/fpga.scm')
| -rw-r--r-- | gnu/packages/fpga.scm | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index ae326b1138..0a5e26f73c 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -214,11 +214,11 @@ For synthesis, the compiler generates netlists in the desired format.") (list bison cxxopts ;header-only library flex - gawk ; for the tests and "make" progress pretty-printing - iverilog ; for the tests + gawk ;for the tests and "make" progress pretty-printing + iverilog ;for the tests pkg-config python - tcl)) ; tclsh for the tests + tcl)) ;tclsh for the tests (inputs (list abc bash-minimal @@ -226,13 +226,13 @@ For synthesis, the compiler generates netlists in the desired format.") gtkwave libffi psmisc + python + python-click readline tcl xdot z3 - zlib - python - python-click)) + zlib)) (home-page "https://yosyshq.net/yosys/") (synopsis "FPGA Verilog RTL synthesizer") (description "Yosys synthesizes Verilog-2005.") |