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| author | Maxim Cournoyer <maxim.cournoyer@gmail.com> | 2024-11-12 14:29:03 +0900 |
|---|---|---|
| committer | Maxim Cournoyer <maxim.cournoyer@gmail.com> | 2024-11-12 17:41:38 +0900 |
| commit | 708313bf3e7e1dcf7898a5e7e11881749cfab2d1 (patch) | |
| tree | 71ac18f3755cc94948de570cc2aab445e44d8dac /gnu/packages/fpga.scm | |
| parent | 98e470d0a5c58dcdae35846de20a18a4916d9d9c (diff) | |
gnu: iverilog: Update home page.
* gnu/packages/fpga.scm (iverilog) [home-page]: Add a trailing slash to please
'guix lint'.
Change-Id: I89d742950f5d55f8b3ce6d221b1337242a01649f
Diffstat (limited to 'gnu/packages/fpga.scm')
| -rw-r--r-- | gnu/packages/fpga.scm | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index c3b6030fb1..e69169b980 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -128,7 +128,7 @@ formal verification.") #:bootstrap-scripts #~(list "autoconf.sh"))) (native-inputs (list autoconf bison flex gperf)) (inputs (list zlib)) - (home-page "https://steveicarus.github.io/iverilog") + (home-page "https://steveicarus.github.io/iverilog/") (synopsis "FPGA Verilog simulation and synthesis tool") (description "Icarus Verilog is a Verilog simulation and synthesis tool. |